How far can we push conventional silicon technology and what are the future alternatives for transistors and interconnects?Date: 2016-10-06 Add to Google Calendar
Time: 7:00pm - 8:30pm
Location: i-Lab (Building 37)
Speaker: Krishna Saraswat, Rickey/Nielsen Chair Professor of Electrical Engineering at Stanford University.
Sponsored by the University of Hawaii IEEE Student Branch and IEEE Hawaii EDS/SSCS Chapter
Silicon has dominated the microelectronics industry in the past. However, future Si technology is reaching practical and fundamental limits. To go beyond these limits novel devices like FinFETs, TunnelFETs, SpinFETs and higher mobility material like Ge and III-Vs are being aggressively studied to continue progress in integrated electronics. Recently Carbon nanotubes (CNT) and 2D materials like graphene, metal sulfides, telurides and selenides have emerged as potential candidates for nanoscale devices.
The scaling paradigm is also threatened by interconnect limits including excessive power dissipation, insufficient bandwidth, and signal latency for both off-chip and on-chip applications. Many of these obstacles stem by the increase in Cu resistivity, as wire dimensions are reduced to nanoscale. This makes it imperative to examine alternate interconnect schemes for future such as CNTs, optical interconnects and 3-D integration.
Is Ge PMOS and III-V NMOS co-integration on Si feasible or a headache for the manufacturing folks? Are CNT and 2D materials more promising? Do the CNTs and graphene interconnects offer significant advantage over Cu/low-k? Will optical interconnects be ever integrated on a chip? This talk will try to answer some of these questions.
Krishna Saraswat is Rickey/Nielsen Chair Professor of Electrical Engineering at Stanford University. He also has an honorary appointment of an Adjunct Professor at the BITS, Pilani, India since January 2004. He received Ph.D. from Stanford University in 1974 and B.E. from BITS in 1968. His research interests are in new and innovative materials, structures, and process technology of silicon, germanium and III-V devices and metal and optical interconnects for nanoelectronics, and high efficiency and low cost solar cells. He has supervised more than 85 doctoral students, 25 post doctoral scholars and has authored or co-authored over 750 technical papers. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000, the 2004 IEEE Andrew Grove, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007 and the Semiconductor Industry Association Researcher of the Year Award in 2012. He is listed by ISI as one of the 250 Highly Cited Authors in his field.